This invention relates to programmable application specific integrated circuits (ASICs) useful for a variety of data processing applications including communication applications.
Communication devices such as cellular telephone handsets, cordless telephones, wireless local area network (WLAN) client stations, and other wired and wireless radio communication devices, require signal processing according to one of a variety of open or proprietary communication standards or protocols. Due to the numerous communication protocols, variations and improvements thereto, being developed, efforts have been made to develop what is referred to as a software defined radio (SDR) device.
The concept behind the SDR device is the ability to reprogram and reconfigure a device with capabilities, such as a new or modified communication protocol, while in an operational environment. These capabilities are also referred to as “waveforms” and include digital signal processing functions, networking protocols, and other algorithms required for communication in accordance with a defined standard.
The modem processing portion of a modern radio device typically includes either one or more field programmable gate array (FPGA(s)) or one or more ASIC device(s) to host the digital signal processing (DSP) functions for the communication standard(s) supported by the device. These DSP functions tend to be very processing intensive and/or have time-critical execution constraints.
FPGA devices are generally used in SDR designs where waveform reprogrammability and reconfigurability, and waveform “download” objectives are important. In this case, when the operator selects a given waveform as his communications media, the radio system loads the FPGA with the necessary DSP algorithms to operate the selected waveform. Likewise, when the operator selects another waveform as the communications medium (i.e., reprograms and re-configures the radio channel), the radio system reloads the FPGA with a different set of DSP algorithms required to operate the newly-selected waveform. The reprogrammability aspects of the FPGA also supports waveform “downloads”, which involves incorporating changes to existing waveforms and adding new waveforms as they become available.
ASIC devices are generally used in radio applications where re-programmability is not required. In this case, ASIC devices are generally built for one specific waveform, or to host well-defined DSP algorithms that may not be practical to implement in an FPGA.
Use of an FPGA in an SDR device has 3 major shortcomings: (1) very high power consumption; (2) large component size due to large silicon area, and (3) high component cost. First, for high speed and performance related designs the FPGA consumes a large amount of power, which is problematic in SDR designs, particularly for battery-operated devices or equipment. To illustrate, for a given waveform design, an FGPA implementation of that design would consume approximately 5 to 10 times the power consumed by a similar design implemented with an ASIC. The relatively high power consumption of the FPGA results in lower battery life for portable radio devices, and significantly complicates the thermal management aspects of the device design.
Second, from a size standpoint, FPGA devices tend to be relatively large devices. Again, for a given waveform, an FGPA sized to support that waveform may be 5 to 10 times the size of an ASIC implementation. This relatively large size negatively impacts the drive towards reducing the size of portable radio devices that are programmable.
Third, from a hardware component standpoint, the unit cost of the FPGA device may be 10 to 20 times that of an ASIC, which drives the overall cost of the radio equipment.
Use of the traditional ASIC devices in low-power, programmable SDR devices also has its disadvantages: (1) inability to be reprogrammed in an operational environment; (2) inability to support the large number of waveforms (e.g., 20-40) needed; and (3) cannot be augmented or enhanced after product introduction for new waveforms.
First, traditional ASIC devices contain waveform functions hard cast in silicon. As such, this type of device is not reprogrammable in an operational environment.
Second, ASIC devices are generally built for one specific waveform, (or to host well-defined DSP algorithms that may not be practical to implement in an FPGA). Therefore, hosting 20–40 different waveforms in one SDR device would require including 20–40 traditional ASIC devices in the device (generally, one per waveform). In this configuration, when the operator selects a waveform, the radio system would “switch in” the ASIC specific to the selected waveform and the other 19–39 ASICs would be “switched out”. This is a relatively impractical from the standpoint of resource optimization and physical size.
Third, traditional ASICs do not have the ability to be reloaded with new waveforms or new DSP algorithms. Once the radio device is built using traditional ASICs, any enhancements, modifications, or added functionality are not possible without replacing the ASIC device. Replacing the ASIC device is neither practical nor cost effective, especially once the device is fielded.
What is needed is a data processing environment that is reconfigurable after deployed in the field, and may be suitable for portable device applications that are constrained by power consumption limitations.